A 5 GHz Direct Digital Synthesizer MMIC with Direct Modulation and Spur Randomization

Abstract-This paper presents a low power, ultra high speed and high resolution SiGe DDS MMIC with 24-bit phase and 10-bit amplitude resolution. The DDS MMIC has the capabilities of direct frequency and phase modulations with 24 bit and 12 bit resolution, respectively. It is the first reported mm-wave DDS with direct digital frequency and phase modulation capabilities. Utilizing a 13-bit built-in ultra high speed pseudorandom binary sequence (PRBS) generator, the DDS MMIC can perform least significant bit (LSB) dithering for spur randomization. With more than twenty thousand transistors, the DDS MMIC includes a 24-bit ripple carry accumulator for phase accumulation, a 12-bit ripple carry adder for phase modulation, an LSB dithering block for spur randomization and a 10-bit segmented sine-weighted DAC for phase to amplitude mapping and digital to analog conversion. The DDS core occupies 3.0×2.5 mm 2 and consumes 4.7 W power under a single 3.3 V power supply. The Nyquist band SFDR is measured as 38 dBc with 469.360351 MHz output under 5.0 GHz maximum clock (FCW = 0x180800). With 1.246258914 GHz output frequency (FCW = 0x3FCFE7), the narrow band SFDR is measured as 82 dBc. The DDS MMIC is packaged and tested in LCC-68 cavity. Index Terms-digital-to-analog converter (DAC), direct digital synthesizer (DDS), direct digital frequency synthesizer (DDFS), sine-weighted digital-to-analog converter, Rom-less DDS, frequency modulation (FM), phase modulation (PM

A 12bit 300MHz Current-Steering CMOS D/A Converter

The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs, trading-off between the precision, speed, and size of the chip. In order to ensure the linearity of the DAC, a double Centro symmetric current matrix is designed by the Q2 random walk strategy. To achieve better dynamic performance, a latch is added in front of the current switch to change the input signal, such as its optimal cross-point and voltage level. For a 12bit resolution,the converter reaches an update rate of 300MHz

A Mouse Model of Enterovirus D68 Infection for Assessment of the Efficacy of Inactivated Vaccine

In recent years, enterovirus D68 (EVD68) has been reported increasingly to be associated with severe respiratory tract infections and acute flaccid myelitis (AFM) in children all over the world. Yet, no effective vaccines or antiviral drugs are currently available for EVD68. Although several experimental animal models have been developed, immunogenicity and protective efficacy of inactivated EVD68 vaccines has not been fully evaluated. To promote the development of vaccines, we established an Institute of Cancer Research (ICR) suckling mouse model of EVD68 infection in this study. The results showed that ICR neonatal mice up to about nine days of age were susceptible to infection with EVD68 clinical strain US/MO/14-18947 by intraperitoneal injection. The infected mice exhibited progressive limb paralysis prior to death and the mortality of mice was age- and virus dose-dependent. Tissue viral load analysis showed that limb muscle and spinal cord were the major sites of viral replication. Moreover, histopathologic examination revealed the severe necrosis of the limb and juxtaspinal muscles, suggesting that US/MO/14-18947 has a strong tropism toward muscle tissues. Additionally, β-propiolactone-inactivated EVD68 vaccine showed high purity and quality and induced robust EVD68-specific neutralizing antibody responses in adult mice. Importantly, results from both antisera transfer and maternal immunization experiments clearly showed that inactivated EVD68 vaccine was able to protect against lethal viral infection in the mouse model. In short, these results demonstrate the successful establishment of the mouse model of EVD68 infection for evaluating candidate vaccines against EVD68 and also provide important information for the development of inactivated virus-based EVD68 vaccines

A 12-bit 300 MHz CMOS DAC for high-speed system applications

This paper describes a 12-bit 300 MHz CMOS DAC for high-speed system applications. The proposed DAC consists of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs. In order to ensure the linearity of DAC, a double Centro symmetric current matrix is designed by using the Q(2) random walk strategy. To minimize the feedthrough and improve the dynamic performance, the drain of the switching transistors is isolated from the output lines by adding two cascoded transistors